Senior/Principal High-Speed Analog Layout Design Engineer

About the role

We are looking for a Principal or Senior Analog Layout Engineer to lead the physical design of high‑performance analog and mixed‑signal IP blocks used in advanced optical communication systems. The role involves end‑to‑end layout development, close collaboration with circuit designers and CAD teams, and ensuring first‑pass silicon success.

Key responsibilities

• Lead and own the layout of complex analog/mixed‑signal macros (e.g., ADCs, DACs, PLLs) from floor planning to final verification.
• Work with schematic designers to optimise performance, matching, symmetry and reliability.
• Mentor junior layout engineers across multiple time zones and enforce best‑practice standards.
• Perform and debug full‑hierarchy LVS, DRC, PERC, ERC and other sign‑off checks using industry tools.
• Contribute to chip‑level planning, including top‑level floor planning, block integration, power‑grid implementation and signal routing.
• Participate in design reviews and provide technical leadership for layout quality and schedule adherence.
• Support automation initiatives through scripting and tool customisation (SKILL, TCL, Python).

Required profile

• 10+ years of hands‑on analog/mixed‑signal layout experience in advanced CMOS/FinFET technologies.
• Proven track record of delivering top‑level IP layout macros and full‑chip integration, preferably on TSMC FinFET nodes (N3, N5, N7, N16).
• Deep understanding of device physics and layout‑dependent effects (LOD, WPE, OSE, LDE).
• Strong expertise in device matching, noise isolation, ESD protection, symmetry and parasitic minimisation.
• Proficiency in floor planning, hierarchical block integration, routing strategy and power/ground grid design.
• Excellent documentation and communication skills for cross‑functional teams.

Required skills

• Cadence Virtuoso
• Calibre
• Pegasus
• SKILL scripting
• TCL
• Python (optional)
• LVS, DRC, PERC, ERC verification flows