Memory Design Engineer – Senior IP Engineer

About the role

The Senior IP Engineer will join Allegro’s Technology Development group to create and verify semiconductor memory IP. Working within the Design Enablement team, you will develop standard IP memories such as SRAM, ROM, EEPROM, and FLASH, supporting the company’s BCD technology and a global design community.

Key responsibilities

• Design and layout NVM, VM, driver circuits, and digital IP using Cadence EDA tools.
• Perform IP-in-silicon test and validation, including silicon testing and debugging.
• Coordinate design requirements, macro floor‑planning, and layout creation.
• Characterize and standardize memory and digital IP for use within a custom PDK environment.
• Develop and publish IP specifications, application use cases, and documentation.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering (BSEE) with at least 2 years of industry experience.
• Hands‑on experience in memory and mixed‑signal transistor‑level design, circuit verification, and silicon testing.
• Ability to create memory test and validation plans and to characterize memory cells in standard liberty format.

Required skills

• Cadence tool flow: Virtuoso, Genus, Innovus, Xcellium, Modus Test, Quantus/Calibre.
• IP characterization tools.
• HDL languages: Verilog, Verilog‑A, Verilog‑AMS; knowledge of C and SystemVerilog is a plus.
• Digital components knowledge: logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial communication protocols, microprocessors, microcontrollers.