DSP Firmware Engineer

About the role

Marvell’s coherent DSP devices enable efficient transmission over fiber‑optic networks. The DSP Firmware Engineer will join a highly skilled team responsible for the design, simulation, implementation, and validation of DSP ASICs used in hyperscale and telecom infrastructures.

Key responsibilities

• Develop RTL for microcontroller subsystems and integrate existing CPU/microprocessor cores.
• Design on‑chip buses, memory interfaces, interrupts, peripherals, and communication blocks.
• Create block‑level specifications and documentation.
• Collaborate with verification teams to define test plans, debug issues, and ensure functional correctness.
• Support synthesis, timing closure, and physical implementation by providing constraints and resolving design issues.

Required profile

• Bachelor’s or Master’s degree in Electronics, Computer Science, or Telecommunications.
• Proficiency in RTL design using Verilog and/or SystemVerilog.
• Strong understanding of digital logic, synchronous design principles, and hardware state machines.
• Experience with simulation and debugging tools such as ModelSim, VCS, or Questa.
• Ability to work collaboratively with verification, physical design, and firmware teams and communicate in English.

Required skills

• Verilog / SystemVerilog RTL coding
• Digital logic and synchronous design
• Simulation tools (ModelSim, VCS, Questa)
• On‑chip bus protocols (AMBA AXI, AHB, APB)
• Integration of microprocessor cores and memory subsystems
• ASIC synthesis and static timing analysis
• Hardware state‑machine design
• Debugging of complex digital IP blocks