Digital IC Design Junior Engineer

About the role

Marvell’s Coherent DSP Business Unit is seeking a Junior Digital IC Design Engineer to join a high‑performance ASIC team. You will contribute to the design, simulation, implementation and validation of DSP ASICs used in hyperscale and telecom networks.

Key responsibilities

• Analyze product specifications and architectural requirements to plan design and verification for high‑speed communication chips.
• Develop RTL modules in Verilog/SystemVerilog, integrating C++, Python and Linux‑based tooling.
• Prototype next‑generation IP blocks to assess feasibility and de‑risk future products.
• Maintain and enhance silicon‑proven RTL and firmware across existing Marvell product lines.
• Define and execute verification strategies, including unit, integration and regression testing using Python‑based frameworks.

Required profile

• Bachelor’s degree in Electronics, Computer, or Telecommunications Engineering.
• Hands‑on experience with digital design and RTL development.
• Familiarity with chip development flows and verification methodologies.
• Ability to work independently and collaboratively in cross‑functional teams.
• Strong analytical and problem‑solving skills.
• English at an intermediate‑advanced level and Spanish native or fluent.

Required skills

• Proficiency in C, C++ and Python.
• Working knowledge of Verilog, SystemVerilog or VHDL.
• Understanding of object‑oriented programming principles.
• Experience with Linux‑based development environments and firmware.

What we offer

• Competitive compensation and comprehensive benefits.
• A collaborative, transparent and inclusive work environment.
• Access to tools and resources that support professional growth.
• Equal‑opportunity employment.