Physical Design Engineer

About the role

Marvell is seeking a Physical Design Engineer to contribute to the development of next‑generation high‑performance processor chips. You will work on cutting‑edge CMOS processes for server, 5G/6G, and networking applications, collaborating with a global team.

Key responsibilities

• Run RTL code through synthesis and place‑and‑route (PnR) tools to generate the physical view of the chip.
• Perform timing analysis and verify performance against specifications.
• Analyze and validate power grids using EMIR analysis.
• Review sign‑off checks, identify errors, and create optimizations for successful runs.
• Develop and refine methodology to improve design efficiency and robustness.

Required profile

• Bachelor’s in Electrical/Computer Engineering, Computer Science, or related field with 1‑3 years experience, or a Master’s/PhD in the same disciplines.
• Completed digital logic coursework and projects involving circuit design, testing, and timing analysis.
• Experience designing and testing logic blocks and evaluating quality of results.
• Strong analytical mindset and willingness to learn through hands‑on work.

Required skills

• RTL coding and synthesis.
• Place‑and‑route (PnR) tools.
• Timing analysis.
• EMIR (power grid) analysis.
• Digital logic design and circuit testing.

What we offer

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Access to mentors and learning resources to accelerate growth.