High-Speed Analog Layout Design Engineer

About the role

We are seeking a High-Speed Analog Layout Design Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high‑performance analog/mixed‑signal circuits while interfacing closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first‑pass silicon success.

Key responsibilities

• Lead and own the physical layout design of complex analog/mixed‑signal macros (e.g., ADCs, DACs, PLLs) from floor planning through final verification.
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices.
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other sign‑off checks using industry‑standard tools (Pegasus, Calibre, etc.).
• Contribute to chip‑level planning including top‑level floor planning, block integration, power grid implementation, and signal routing.
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence.
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python).

Required profile

• Minimum 1+ years of hands‑on analog/mixed‑signal layout design experience in advanced CMOS/FinFET technologies.
• Proven track record of delivering top‑level IP layout macros and preparing IPs for handoff to Physical Design.
• Experience with TSMC FinFET process nodes (N3, N5, N7, or N16) and deep understanding of device physics and layout‑dependent effects.
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.
• Excellent documentation and communication skills for presenting layout trade‑offs to cross‑functional teams.

Required skills

• Cadence Virtuoso
• Calibre
• Pegasus
• TSMC FinFET nodes (N3, N5, N7, N16)
• LVS, DRC, PERC, DFM, ERC, Antenna verification
• SKILL, TCL, Python scripting
• Revision control systems for layout management

What we offer

• The chance to play a foundational role at a high‑growth semiconductor start‑up.
• Exposure to a wide variety of cross‑functional teams.
• A collaborative, international team culture where ideas and initiative are valued.
• Opportunity to grow alongside Celero as we scale and shape the future of AI and data‑center connectivity.