Digital IC Design Junior Engineer

About the role

Join Marvell's Coherent DSP Business Unit to design high‑performance integrated circuits for leading hyper‑scale and telecom networks. You will work on the full lifecycle of DSP ASICs, from specification analysis to validation.

Key responsibilities

• Analyze product specifications and architectural requirements to plan design and verification for high‑speed communication chips.
• Develop RTL modules in Verilog/SystemVerilog and integrate C++, Python, and Linux‑based tooling.
• Prototype next‑generation IP blocks to assess feasibility and de‑risk future products.
• Maintain and enhance silicon‑proven RTL and firmware across existing Marvell product lines.
• Develop and execute verification strategies, including unit, integration, and regression testing using Python frameworks.

Required profile

• Bachelor's degree in Electronics, Computer, or Telecommunications Engineering.
• Hands‑on experience in digital design and RTL development.
• Familiarity with chip development flows and verification methodologies.
• Ability to work independently and collaboratively in cross‑functional teams.

Required skills

• Proficiency in C, C++, and Python.
• Working knowledge of Verilog, SystemVerilog, or VHDL.