Physical Design Engineer

About the role

Join Marvell’s custom Processor/ASIC team to design next‑generation high‑performance processor chips in leading‑edge CMOS technology. You will work on both the physical design and the methodology that enables efficient, robust chip development for server, 5G/6G, automotive and networking applications.

Key responsibilities

• Run RTL code through synthesis and place‑and‑route (PnR) tools to generate the physical view of the chip.
• Perform timing analysis and verify performance against specifications.
• Validate power‑grid robustness using EMIR analysis.
• Review sign‑off checks, identify errors and create optimizations from successful runs.
• Collaborate with a global team to improve design workflows and methodology.

Required profile

• Bachelor’s (1‑3 years experience) or Master’s/PhD in Electrical/Computer Engineering, Computer Science or related field.
• Completed digital‑logic coursework and projects involving circuit design, testing and timing analysis.
• Experience designing and testing logic blocks and analyzing quality of results.
• Proactive learning attitude and willingness to take on new challenges.

Required skills

• RTL synthesis and place‑and‑route tools.
• Timing analysis formulas and concepts.
• EMIR (electromigration) analysis for power‑grid verification.
• Understanding of CMOS process technology.

What we offer

• Eligibility for Marvell’s bonus and equity plans, including new‑hire equity grant and annual refreshers.
• Competitive compensation and comprehensive benefits in a collaborative, inclusive environment.