ASIC Design Engineer

About the role

Celero is looking for experienced ASIC Design Engineers to develop cutting‑edge optical transceivers for next‑generation modems. You will be responsible for creating high‑performance digital ASICs and collaborating with cross‑functional teams to bring innovative solutions to market.

Key responsibilities

• Design and implement digital circuits using Verilog or SystemVerilog.
• Perform synthesis, timing analysis, lint, formal equivalence, and clock‑domain‑crossing (CDC) analysis.
• Optimize designs for performance, power, and area (PPA) targets.
• Run RTL simulations and verification to ensure functional correctness.
• Participate in design reviews and provide technical guidance to teammates.
• Collaborate with system integration and validation teams across hardware and software domains.

Required profile

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in digital ASIC design and verification.
• Strong understanding of digital design principles, low‑power techniques, and ASIC design flow.
• Experience with verification methodologies such as UVM or formal verification.
• Excellent problem‑solving, communication, and teamwork abilities.

Required skills

• Verilog / SystemVerilog (HDL)
• Synthesis, timing analysis, lint, formal equivalence, CDC analysis
• PPA optimization
• RTL simulation and verification
• UVM and formal verification methodologies
• Low‑power design techniques
• Python and Tcl scripting
• Digital Signal Processing (DSP)
• Digital Communication and Forward Error Correction (FEC) concepts